Omschrijving

I am a DSP algorithm-to-silicon engineer and senior digital IC design and verification engineer, with a PhD from Ghent University / imec and 11+ years of experience bridging high-speed DSP algorithms and silicon implementation.

My background spans wireless and optical communications (massive MIMO, sigma-delta modulation, PAM-4), image sensor ICs (MIPI D-PHY/C-PHY, gate-level simulation), FPGA prototyping, and full ASIC flow from RTL to silicon bring-up. I have delivered 6 successful tapeouts (TSMC 28nm & 90nm) and achieved a real-time 100 GS/s sigma-delta modulator — a world record at publication time.

I offer freelance services in:

- FPGA design & DSP implementation (Xilinx/AMD, SystemVerilog, VHDL, MATLAB-to-RTL)

- Digital IC design (SystemVerilog, Verilog, RTL, Synthesis, Linting, LEC etc.)

- Digital IC verification (UVM full flow, Regmap, regression and coverage, Cadence Xcelium/IMC, Synopsys VCS/Verdi)

- Algorithm-to-hardware implementation (sigma-delta, MIMO, high-speed filters (FIR, IIR), equalization etc.)

Available remotely worldwide and on-site in Belgium and the Netherlands. Belgian citizen based in Ghent. Fluent in English and Dutch.

Branche-expertise

Talen

Engels
Tweetalig / moedertaal
Nederlands
Vloeiend
Chinees
Tweetalig / moedertaal

Voorkeuren voor werkplek

Uitsluitend remote

Werkt voornamelijk remote

Gpixel,
Senior Digital Design & Verification Engineer
december 2024 - juni 2026 (1 jaar en 6 maanden)
Antwerp, Belgium
• • Digital verification of high-resolution image sensor ICs; 2 successful tapeouts in 90nm
• • Full UVM verification flow: coverage plan, testbench architecture, test case development, regression, coverage holes analysis and closure (Cadence Xcelium / IMC)
• • Gate-level simulation with SDF timing annotation
• • MIPI D-PHY and C-PHY protocol verification (high-speed serial interface for camera-to-SoC data transmission)
• • Conformal LEC (Logical Equivalence Checking) for RTL vs netlist sign-off
• • RTL design of digital modules in VHDL
Conformal LEC Cadence Xcelium Cadence IMC UVM verification Post-layout gate-level simulation with SDF
iCana BV,
Senior Digital IC Architect
TELECOMMUNICATIE
oktober 2022 - oktober 2024 (2 jaren)
Leuven, Belgium
• • 3 successful tapeouts in TSMC 28nm (mmWave beamforming and up-/down-converter ICs)
• • Captured design requirements from RF/system teams; proposed system architecture and digital design specifications
• • RTL design, simulation, and modeling in SystemVerilog, MATLAB, and C
• • Full UVM verification ownership: verification plan, RAL register model, functional test cases, regression, coverage (Synopsys VCS/Verdi/URG), C reference model
• • Register map automation: Excel to RTL, RALF, C header, HTML documentation
• • Third-party IP (eFuse, SRAM, PoR) integration and UVM verification
• • Synthesis, LEC, and post-synthesis/layout simulation with SDF (20 corners), X-propagation
• • Digital mixed-signal UVM environment setup; AMS team collaboration
• • Backend coordination: floorplan, UPF, DFT, MBIST, IDDQ, ATPG, ECO
• • Silicon bring-up: register/SRAM/eFuse regression, functional test vs UVM reference model
• • Python demo UI development for customer demonstrations
Verdi Formality LEC SpyGlass Lint VCS SystemVerilog
imec - Ghent University (IDLab),
Senior Researcher
TELECOMMUNICATIE
september 2014 - oktober 2022 (8 jaren en 1 maand)
Belgium
• • 1 successful ASIC tapeout in TSMC 28nm: mixed-signal CDR and high-speed DSP chip for 28 GBaud PAM-4 optical links
◦ - 1.75 GHz digital clock (equivalent 7/14 GHz)
◦ - key blocks: preamble synchronisation, high-speed FIR filter, IIR filter pipelining (zero-poles insertion), 14 GS/s sigma-delta modulator (baseband and passband), async FIFO for CDC
◦ - post-synthesis/layout sim with SDF and jittered clocks, SDC constraints, X-propagation
◦ - Synthesis flow, floorpan, partitioning, timing/congestion optimization
◦ - Silicon bring-up test and performance measurement with FPGA platform
• • Bridged algorithm and silicon: translated massive MIMO precoding, sigma-delta modulation, and synchronisation algorithms from MATLAB specification to real-time FPGA/ASIC implementation for UGent imec cell-free massive MIMO testbed (EU ERC ATTO / Horizon 2020 Int5Gent)
• • Achieved real-time 100 GS/s sigma-delta modulator (world record at publication, 2019 OFC Top Scored); implemented timing recovery, fractional-delay interpolation, high-speed IIR/FIR filter design on FPGA/ASIC
• • Developed MATLAB/Python reference models for MIMO antenna calibration, MIMO precoding, and self interference cancellation; used as golden reference for ASIC and FPGA validation
• • 8 years FPGA/RTL design in Vivado and Cadence Xcelium/Genus; Xilinx IPs (PCIe, GTY, MicroBlaze, AXI4, DDR4); SystemVerilog
• • Supervised 4 master theses; demonstrated real-time optical/wireless communication systems live at OFC and ECOC international conferences
DSP FPGA Cadence Xcelium Cadence Genus Digital IC design